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sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 1 - table of contents product list .......................................................................................................................................................................... 3 description ........................................................................................................................................................................... 3 features ............................................................................................................................................................................... 3 pin configuration ................................................................................................................................................................. 4 block diagram ...................................................................................................................................................................... 5 pin description ..................................................................................................................................................................... 6 special function register (sfr) ......................................................................................................................................... 7 function description .......................................................................................................................................................... 10 1. general features ........................................................................................................................................................ 10 1.1. embedded flash .......................................................................................................................................... 10 1.2. io pads ........................................................................................................................................................ 10 1.3. instruction timing select ion .......................................................................................................................... 10 1.4. the clock output selection .......................................................................................................................... 11 1.5. reset .......................................................................................................................................................... 11 1.5.1. h ardware reset function ............................................................................................................... 11 1.5.2. software reset function ................................................................................................................ 11 1.5.3. reset status ..................................................................................................................................... 11 1.5.4. time access key register (takey) ................................................................................................. 12 1.5.5. software reset register (swres) .................................................................................................. 12 1.5.6. example of softwa re reset .............................................................................................................. 12 1.6. clocks .......................................................................................................................................................... 12 2. instruction set ............................................................................................................................................................. 14 3. memory struc ture ........................................................................................................................................................ 18 3.1. program memory ......................................................................................................................................... 18 3.2. data memory ................................................................................................................................................ 19 3.2.1. data m emory - lower 128 byte (00h to 7fh) ................................................................................... 19 3.2.2. data memory - higher 128 byte (80h to ffh) ................................................................................. 19 4. cpu engine ................................................................................................................................................................. 20 4.1. accumulator ................................................................................................................................................. 20 4.2. b register .................................................................................................................................................... 20 4.3. program status word ................................................................................................................................... 21 4.4. stack pointer ................................................................................................................................................ 21 4.5. data pointer ................................................................................................................................................. 21 4.6. data pointer 1 .............................................................................................................................................. 22 4.7. interface control register .............................................................................................................................. 22 5. gpio ............................................................................................................................................................................ 23 5.1. sfr setting method ..................................................................................................................................... 2 3 5.2. software of writer setting method ............................................................................................................... 23 6. timer 0 and timer 1 .................................................................................................................................................... 24 6 .1. timer/counter mode control register (tmod) .............................................................................................. 24 6.2. timer/counter control register (tcon) ........................................................................................................ 25 6.3. enhance interrupt trigger s fr(enhit) ....................................................................................................... 25 6.4. t0 t1 signal swapping .............................................................................................................................. 26 7. serial interface ............................................................................................................................................................ 27 7.1. mode 0 ......................................................................................................................................................... 28 7.2 . mode 1 ......................................................................................................................................................... 28 7.3. mode 2 ......................................................................................................................................................... 29 7.4. mode 3 ......................................................................................................................................................... 29 7.5. multiprocessor co mmunication .................................................................................................................... 29 7.6. baud rate generator ..................................................................................................................................... 30 8. watchdog timer ........................................................................................................................................................... 31 9. interrupt ....................................................................................................................................................................... 35 10. power management unit ............................................................................................................................................. 40 10.1. idle mode ..................................................................................................................................................... 40
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 2 - 10.2. stop mode .................................................................................................................................................... 40 11. pwm - pulse width modulation .................................................................................................................................. 41 12. iic function .................................................................................................................................................................. 44 13. lvi ? low voltage interrupt ......................................................................................................................................... 48 14. 10- bit analog - to - digital converter (adc) .................................................................................................................... 49 15. eeprom ..................................................................................................................................................................... 52 16. comparator ................................................................................................................................................................. 54 dc characteristics ............................................................................................................................................................. 56 adc characteristics .......................................................................................................................................................... 58 comparator characteristics ............................................................................................................................................... 58 lvi& lvr characteristics ................................................................................................................................................... 58
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 3 - product list sm39 r0 8a5 u 10mp description the sm39 r08a5 i s a 1t (one machine cycle per clock) single - chip 8 - bit microcontroller. it has 8 k - byte embedded flash for program, and executes all asm51 instructions fully compatible with mcs - 51. sm39 r08a5 contains 256b on - chip ram, up to 8 gpios ( 10 l package), various s erial interfaces and many peripheral functions as described below. it can be programmed via writers. its on - chip ice is convenient for users in verification during development stage. the high performance of sm39 r08a5 can achieve complicated manipulation within short time. about one third of the instructions are pure 1t, and the average speed is 8 times of traditional 8051, the fastest one among all the 1t 51 - series.its excellent emi and esd characteristics are advantageous for many different applications. ordering information sm39 r0 8a5 ihhkl yww i: process identifier { u = 1.8 v ~ 5.5v} hh: pin count k: package type postfix {as table below } l:pb free identifier {no text is non - pb free ?p? is pb free} y : year ww : week postfix package pin / pad configurati on m msop (118 mil) page 4 features ? operating voltage: 1.8v ~ 5.5v ? 1~8t modes are software programmable. ? instruction - set compatible with mcs - 51. ? 22.1184mhz internal rc oscillator, with programmable clock divider ? 8 k bytes on - chip flash progr am memory. ? 256 bytes ram as standard 8052, ? one serial peripheral interfaces in full duplex mode. 1.1 synchronous mode, fixed baud rate, 1.2 8 - bit uart mode, variable baud rate. 1.3 9 - bit uart mode, fixed baud rate, 1.4 9 - bit uart mode, variable baud rate. ? additional baud rate generator ? two 16 - bit timer/counters. (timer 0, 1) ? 8 gpios( 1 0 l m sop) ? programmable watchdog timer. ? one iic interface. (master/slave mode) ? 10 bit pwm x 4 channel ? 8 channel 10 - bit an alog - to - digital converter (adc) ? on - chip comparator x 1 ? on ? chip flash memo ries support iap/icp and eeprom functions. ? on - chip in - circuit emulator (ice) functions with on - chip debugger (ocd). ? emi reduction mode (ale output inhibited). ? lvi/lvr. ? io pad esd over 4kv. ? enhance user code protection. ? external interrupt 0, 1 with four pri ority levels. ? power management unit for idle and power down modes.
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 4 - pin configuration 1 0 pin msop 10 9 8 7 vcc p3.7/int1_0/cmp0out/adc7 p3.4/int0_0/sda/adc4 6 p3.5/int1_1/pwm1/scl/clkout/adc5 p3.6/pwm0/reset/adc6 (10 pin top view) txd/adc1/cmp0pin/t1_2/p3.1 1 2 3 4 rxd/adc0/cmp0nin/t0_2/p3.0 adc2/pwm3/t1_1/p3.2 5 vss adc3/pwm2/t0_1/p3.3 r08a5 notes 1. the pin reset/p3.6 factory default is gpio (p3.6). user can configure it to r eset by a flash programmer.
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 5 - block diagram pwm flash 8 kbytes sram 256 bytes interrupt timer 0 / 1 watchdog ice icp port 3 port 3 t 0 t 1 scl pwm 0 ~ 3 interface control int 0 / 1 sda cpu iic scl sda max 810 reset uart rxd txd analog comparator cmp 0 out cmp 0 nin cmp 0 pin adc adc [ 7 : 0 ]
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 6 - pin description 10 pin symbol i/o description 1 - p3.0 - rxd - t0_2 - cmp0nin - adc0 i/o - bit 0 of port 3 - serial interface receive data - timer 0 external input 2 - comparator 0 negative input - adc input channel 0 2 - p3.1 - txd - t1_2 - cmp0pin - adc1 i/o - bit 1 of port 3 - serial interface transmit data - timer 1 external input 2 - comparator 0 positive input - adc input channel 1 3 - p3.2 - pwm3 - adc2 - t1_1 i/o - bit 2 of port 3 - pwm c hannel 3 - adc input channel 2 - timer 1 external input 1 4 - p3.3 - pwm2 - adc3 - t0_1 i/o - bit 3 of port 3 - pwm channel 2 - adc input channel 3 - timer 0 external input 1 5 vss i power supply 6 - p3.4 - int0_0 - sda - adc4 i/o - bit 4 of port 3 - ex ternal interrupt 0 - iic sda pin & on - chip instrumentation command and data i/o pin synchronous to scl in ice and icp functions - adc input channel 4 7 - p3.5 - int1_1 - pwm1 - scl - clkout - adc5 i/o - bit 5 of port 3 - external interrupt 1 - pwm channel 1 - iic scl pin & on - chip instrumentation clock i/o pin of ice and icp functions - clock output - adc input channel 5 8 - p3.6 - reset - pwm0 - adc6 i/o - bit 6 of port 3 - reset pin - pwm channel 0 - adc input channel 6 9 - p3.7 - int1_0 - cmp0out - ad c7 i/o - bit 7 of port 3 - external interrupt 1 - comparator 0 output - adc input channel 7 10 vdd i power supply
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 7 - special function register (sfr) a map of the special function registers is shown as below: hex \ bin x000 x001 x010 x011 x100 x101 x110 x1 11 bin/hex f8 iics iicctl iica1 iica2 iicrwd iicebt cmp0con ff f0 b oppin takey f7 e8 ef e0 acc ispfah ispfal ispfd ispfc lvc swres e7 d8 p3m0 p3m1 df d0 psw d7 c8 pwmmdh pwmmdl cf c0 ircon c7 b8 ien1 ip1 srelh pwmd0h pwmd0l pwmd1h pwmd1l bf b0 p3 pwmd2h pwmd2l pwmd3h pwmd3l pwmc wdtc wdtk b7 a8 ien0 ip0 srell adcc1 adcc2 adcdh adcdl adccs af a0 rsts a7 98 scon sbuf ien2 9f 90 aux ircon2 9 7 88 tcon tmod tl0 tl1 th0 th1 ckcon ifcon 8f 80 sp dpl dph dpl1 dph1 pcon 87 note: special function registers reset values and description for sm39 r 08a5 register location reset value description sp 81h 07h stack pointer dpl 82h 00h data pointer 0 low byte dph 83h 00h data pointer 0 high byte dpl1 84h 00h data pointer 1 low byte dph1 85h 00h data pointer 1 high byte pcon 87h 00h power control tcon 88h 00h timer/counter control tmod 89h 00h timer mode control tl0 8ah 00h timer 0, low byte t l1 8bh 00h timer 1, low byte th0 8ch 00h timer 0, high byte th1 8dh 00h timer 1, high byte ckcon 8eh 10h clock control register ifcon 8fh 00h interface control register aux 91h 00h auxiliary register
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 8 - s con 98h 00h serial port control register s buf 99 h 00h serial port data buffer ien2 9ah 00h interrupt enable register 2 rsts a1h 00h reset status register ien0 a8h 00h interrupt enable register 0 ip0 a9h 00h interrupt priority register 0 s rell aah 00h serial port reload register, low byte adcc1 abh 00h adc control 1 register adcc2 ach 00h adc control 2 register adcdh adh 00h adc data high byte adcdl aeh 00h adc data low byte adccs afh 00h adc clock select p3 b0h ffh port 3 pwmd2h b1h 00h pwm 2 data register high byte pwmd2l b2h 00h pwm 2 data register low byte pwmd3h b3h 00h pwm 3 data register high byte pwmd3l b4h 00h pwm 3 data register low byte pwmc b5h 00h pwm control register wdtc b6h 04h watchdog timer control register wdtk b7h 00h watchdog timer refresh key. ien1 b8h 00h interrupt enable register 1 ip1 b9h 00h interrupt priority register 1 s relh bah 00h serial port reload register, high byte pwmd0h bch 00h pwm 0 data register high byte pwmd0l bdh 00h pwm 0 data register low byte pwmd1h beh 00h pwm 1 data register high byte pw md1l bfh 00h pwm 1 data register low byte ircon c0h 00h interrupt request control register pwmmdh ceh 00h pwm max data register, high byte. pwmmdl cfh 00h pwm max data register, low byte. psw d0h 00h program status word p3m0 dah 00h port 3 output mode 0 p3m1 dbh 00h port 3 output mode 1 acc e0h 00h accumulator ispfah e1h 0fh isp flash address - high register ispfal e2h ffh isp flash address - low register ispfd e3h ffh isp flash data register ispfc e4h 00h isp flash control register lvc e6h 20h low voltage control register swres e7h 00h software reset register b f0h 00h b register oppin f6h 00h op/cmp pin select takey f7h 00h time access key register
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 9 - iics f8h 00h iic status register iicctl f9h 04h iic control register iica1 fah a0h iic channel address 1 register iica2 fbh 60h iic channel address 2 register iicrwd fch 00h iic channel read / write data buffer iicebt fdh 00h iic enable bus transaction cmp0con feh 00h comparator 0 control
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 10 - function description 1. general features sm39 r0 8a5 is an 8- bit micro - controller . all of its functions and the detailed meanings of sfr will be given in the following sections . 1.1. embedded flash the program can be loaded into the embedded 8 kb flash memory via its writer . the high - quality flash suitable for re - p rogramming and data recording as eeprom . 1.2. io pads the sm39 r0 8a5 has an i/o port : port 3 . port 3 is 8 - bit port . these are: quasi - bidirectional (standard 8051 port outputs), push - pull, open drain, and input - only. as descri bed in section 5 . the reset pin c a n b e configured as i/o port p3.6 , when the user use s on- chip hardware reset mechanism . 1.3. instruction timing selection the conventional 52 - series mcus are 12t, i.e., 12 oscill ator clocks per machine cycle. sm39 r0 8a5 is a 1t to 8t mcu, i.e., its machine cycl e is one - clock to eight - clock. in the other words, it can execute one instruction within one clock to only eight clocks. mnemonic: ckcon address: 8eh 7 6 5 4 3 2 1 0 reset - its - - clkout 10h its: instruction timing select. its [6:4] instruction timi ng 000 1t mode 001 2t mode (default) 010 3t mode 011 4t mode 100 5t mode 101 6t mode 110 7t mode 111 8t mode the default is in 2t mode, and it can be changed to another instruction timing mode if ckcon [6:4] (at address 8eh) is change any time. not every instruction can be executed with one machine cycle. the exact machine cycle number for all the instructions are given in the next section.
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 11 - 1.4. the clock out put selection the sm39 r0 8a5 can g enerat e a clock out put signal at p3. 5 . the ckcon [1: 0] (at address 8eh) can change any time. clkout: clock output select. ckcon [1:0] mode. 00 gpio (p3.5) 01 fosc 10 fosc/2 11 fosc/4 1.5. reset 1.5.1. hardware reset function sm39 r08a5 provides on - chip hardware reset mechanism, the reset duration is programma ble by writer or i c p . on - chip hardware reset duration 25ms (default) 200ms 100ms 50ms 16ms 8ms 4ms 1.5.2. software reset function sm39 r08a5 provides one software reset mechanism to reset whole chip. to perform a software reset, the firmware must write three specific values 55h, aah and 5ah sequentially to the takey register to enable the software reset register (swres) write attribute. after swres register obtain the write authority, the firmware can write ffh to the swres register. the hardware will de code a reset signal that ?or? with the other hardware reset. the swres register is self - reset at the end of the software reset procedure. mnemonic description direct bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset software reset function takey tim e access key register f7h takey [7:0] 00h swres software reset register e7h swres [7:0] 00h 1.5.3. reset status mnemonic: rsts address: a1h 7 6 5 4 3 2 1 0 reset - - - pdrf wdtf swrf lvrf porf 00h pdrf: pad reset flag. when mcu is reset by reset pad, pdrf flag will be set to one by hardware. this flag clear by software. wdtf: watchdog timer reset flag. when mcu is reset by watchdog, wdtf flag will be set to one by hardware. this flag clear by software. swrf: software reset flag. when mcu is reset by soft ware, swrf flag will be set to one by hardware. this flag
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 12 - clear by software. lvrf: low voltage reset flag. when mcu is reset by lvr, lvrf flag will be set to one by hardware. this flag clear by software. porf: power on reset flag. when mcu is reset by po r, porf flag will be set to one by hardware. this flag clear by software. 1.5.4. time access key register (takey) mnemonic: takey address: f7h 7 6 5 4 3 2 1 0 reset takey [7:0] 00h software reset register (swres) is read - only by default; software must writ e three specific values 55h, aah and 5ah sequentially to the takey register to enable the swres register write attribute. that is: mov takey, #55h mov takey, #0aah mov takey, #5ah 1.5.5. software reset register (swres) mnemonic: swres address: e7h 7 6 5 4 3 2 1 0 reset swres [7:0] 00h swres [7:0]: software reset register bit. these 8 - bit is self - reset at the end of the reset procedure. swres [7:0] = ffh, software reset. swres [7:0] = 00h ~ feh, mcu no action. 1.5.6. example of software reset mov takey, #55h mov takey, #0aah mov takey, #5ah ; enable swres write attribute mov swres, #0ffh ; software reset mcu 1.6. clocks the default clock is the 22.1184mhz internal osc. this clock is used during the initialization stage. the major work of the initialization stage is t o determine the clock source used in normal operation. the internal clock sources are from the internal osc with difference frequency division as given in t able 1 - 1 , the clock source can set by writer or icp. table 1 - 1: selection of clock source clock source 22.1184mhz from internal osc 11 . 0592 mhz from internal osc 5 . 5296 mhz from internal osc 2.7648 mhz from internal osc 1.3824 mhz from internal osc
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 13 - there may be having a little variance in the frequency from the internal osc. th e max variance as g iving in table 1 - 2 table 1 - 1 : temperature with variance temperature max variance 25 2 %
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 14 - 2. instruction set all sm39 r08a5 instructions are binary code compatible and perform the s ame functions as they do with the industry standard 8051. the following tables give a summary of the instruction set cycles of the sm39 r08a5 microcontroller core. table 2 - 1: arithmetic operations mnemonic description code bytes cycles add a,rn add regist er to accumulator 28 - 2f 1 1 add a,direct add direct byte to accumulator 25 2 2 add a,@ri add indirect ram to accumulator 26 - 27 1 2 add a,#data add immediate data to accumulator 24 2 2 addc a,rn add register to accumulator with carry flag 38 - 3f 1 1 add c a,direct add direct byte to a with carry flag 35 2 2 addc a,@ri add indirect ram to a with carry flag 36 - 37 1 2 addc a,#data add immediate data to a with carry flag 34 2 2 subb a,rn subtract register from a with borrow 98 - 9f 1 1 subb a,direct subtrac t direct byte from a with borrow 95 2 2 subb a,@ri subtract indirect ram from a with borrow 96 - 97 1 2 subb a,#data subtract immediate data from a with borrow 94 2 2 inc a increment accumulator 04 1 1 inc rn increment register 08 - 0f 1 2 inc direct incr ement direct byte 05 2 3 inc @ri increment indirect ram 06- 07 1 3 inc dptr increment data pointer a3 1 1 dec a decrement accumulator 14 1 1 dec rn decrement register 18 - 1f 1 2 dec direct decrement direct byte 15 2 3 dec @ri decrement indirect ram 16 - 17 1 3 mul ab multiply a and b a4 1 5 div divide a by b 84 1 5 da a decimal adjust accumulator d4 1 1
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 15 - table 2 - 2: logic operations mnemonic description code bytes cycles anl a,rn and register to accumulator 58 - 5f 1 1 anl a,direct and direct byte to accumulator 55 2 2 anl a,@ri and indirect ram to accumulator 56- 57 1 2 anl a,#data and immediate data to accumulator 54 2 2 anl direct,a and accumulator to direct byte 52 2 3 anl direct,#data and immediate data to direct byte 53 3 4 orl a,rn or regist er to accumulator 48- 4f 1 1 orl a,direct or direct byte to accumulator 45 2 2 orl a,@ri or indirect ram to accumulator 46 - 47 1 2 orl a,#data or immediate data to accumulator 44 2 2 orl direct,a or accumulator to direct byte 42 2 3 orl direct,#data or immediate data to direct byte 43 3 4 xrl a,rn exclusive or register to accumulator 68 - 6f 1 1 xrl a,direct exclusive or direct byte to accumulator 65 2 2 xrl a,@ri exclusive or indirect ram to accumulator 66- 67 1 2 xrl a,#data exclusive or immediate dat a to accumulator 64 2 2 xrl direct,a exclusive or accumulator to direct byte 62 2 3 xrl direct,#data exclusive or immediate data to direct byte 63 3 4 clr a clear accumulator e4 1 1 cpl a complement accumulator f4 1 1 rl a rotate accumulator left 23 1 1 rlc a rotate accumulator left through carry 33 1 1 rr a rotate accumulator right 03 1 1 rrc a rotate accumulator right through carry 13 1 1 swap a swap nibbles within the accumulator c4 1 1
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 16 - table 2 - 3: data transfer mnemonic description code bytes cycles mov a,rn move register to accumulator e8 - ef 1 1 mov a,direct move direct byte to accumulator e5 2 2 mov a,@ri move indirect ram to accumulator e6 - e7 1 2 mov a,#data move immediate data to accumulator 74 2 2 mov rn,a move accumulator to registe r f8 - ff 1 2 mov rn,direct move direct byte to register a8 - af 2 4 mov rn,#data move immediate data to register 78- 7f 2 2 mov direct,a move accumulator to direct byte f5 2 3 mov direct,rn move register to direct byte 88 - 8f 2 3 mov direct1,direct2 move d irect byte to direct byte 85 3 4 mov direct,@ri move indirect ram to direct byte 86 - 87 2 4 mov direct,#data move immediate data to direct byte 75 3 3 mov @ri,a move accumulator to indirect ram f6 - f7 1 3 mov @ri,direct move direct byte to indirect ram a 6 - a7 2 5 mov @ri,#data move immediate data to indirect ram 76 - 77 2 3 mov dptr,#data16 load data pointer with a 16 - bit constant 90 3 3 movc a,@a+dptr move code byte relative to dptr to accumulator 93 1 3 movc a,@a+pc move code byte relative to pc to acc umulator 83 1 3 push direct push direct byte onto stack c0 2 4 pop direct pop direct byte from stack d0 2 3 xch a,rn exchange register with accumulator c8 - cf 1 2 xch a,direct exchange direct byte with accumulator c5 2 3 xch a,@ri exchange indirect ram with accumulator c6 - c7 1 3 xchd a,@ri exchange low - order nibble indir. ram with a d6 - d7 1 3
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 17 - table 2 - 4: program branches mnemonic description code bytes cycles acall addr11 absolute subroutine call xxx11 2 6 lcall addr16 long subroutine call 12 3 6 ret from subroutine 22 1 4 reti from interrupt 32 1 4 ajmp addr11 absolute jump xxx01 2 3 ljmp addr16 long iump 02 3 4 sjmp rel short jump (relative addr.) 80 2 3 jmp @a+dptr jump indirect relative to the dptr 73 1 2 jz rel jump if accumulator is zer o 60 2 3 jnz rel jump if accumulator is not zero 70 2 3 jc rel jump if carry flag is set 40 2 3 jnc jump if carry flag is not set 50 2 3 jb bit,rel jump if direct bit is set 20 3 4 jnb bit,rel jump if direct bit is not set 30 3 4 jbc bit,direct rel j ump if direct bit is set and clear bit 10 3 4 cjne a,direct rel compare direct byte to a and jump if not equal b5 3 4 cjne a,#data rel compare immediate to a and jump if not equal b4 3 4 cjne rn,#data rel compare immed. to reg. and jump if not equal b8 - bf 3 4 cjne @ri,#data rel compare immed. to ind. and jump if not equal b6 - b7 3 4 djnz rn,rel decrement register and jump if not zero d8 - df 2 3 djnz direct,rel decrement direct byte and jump if not zero d5 3 4 nop no operation 00 1 1 table 2 - 5: boolea n manipulation mnemonic description code bytes cycles clr c clear carry flag c3 1 1 clr bit clear direct bit c2 2 3 setb c set carry flag d3 1 1 setb bit set direct bit d2 2 3 cpl c complement carry flag b3 1 1 cpl bit complement direct bit b2 2 3 anl c,bit and direct bit to carry flag 82 2 2 anl c,/bit and complement of direct bit to carry b0 2 2 orl c,bit or direct bit to carry flag 72 2 2 orl c,/bit or complement of direct bit to carry a0 2 2 mov c,bit move direct bit to ca rry flag a2 2 2 mov bit,c move carry flag to direct bit 92 2 3
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 18 - 3. memory structure the sm39 r08a5 memory structure follows general 8052 structure. it is 8 kb program memory. 3.1. program memory the sm39 r0 8a5 has 8 kb on - chip flash memory which can be us ed as general program memory or eeprom. the address range for the 8 k byte is $ 0 000 to $ 1 fff. it can be used to record any data as eeprom. the procedure of this eeprom application function is described in the section 15 . 1fff 0000 8k program memory space fg 1 m 0 8 programmae fas
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 19 - 3.2. data memory the sm39 r 08a5 has 256bytes on - chip sram; 256 bytes of it are the same as general 8052 internal memory structure higher 128 bytes ( accessed by indirect addressing mode only ) lower 128 bytes ( accessed by direct & indirect addressing mode ) sfr ( accessed by direct addressing mode only ) 00 7 f 80 ff 80 ff fg m arcecre 3.2.1. data memory - lower 128 byte (00h to 7fh) data memory 00h to ffh is the same as 8052. the address 00h to 7fh can be accessed by direct and indirect addressing modes. address 00h to 1fh is register area. address 20h to 2fh is memory bit area. address 30h to 7fh is for general memory area . 3.2.2. data memory - higher 128 byte (80h to ffh) the address 80h to ffh can be accessed by indirect addressing mode. address 80h to ffh is data area.
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 20 - 4. cpu engine the sm39 r 08a5 engine is composed of four components: a. control unit b. arithmetic ? logic unit c. mem ory control unit d. ram and sfr control unit the sm39 r0 8a5 engine allows to fetch instruction from program memory and to execute using ram or sfr. the following chapter describes the main engine register. mnemonic description direct bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset 8051 core acc accumulator e0h acc.7 acc.6 acc.5 acc.4 acc.3 acc.2 acc.1 acc.0 00h b b register f0h b.7 b.6 b.5 b.4 b.3 b.2 b.1 b.0 00h psw program status word d0h cy ac f0 rs[1:0] ov psw.1 p 00h sp stack pointer 81h sp[7: 0] 07h dpl data pointer low 0 82h dpl[7:0] 00h dph data pointer high 0 83h dph[7:0] 00h dpl1 data pointer low 0 84h dpl1[7:0] 00h dph1 data pointer high 0 85h dph1[7:0] 00h aux auxiliary register 91h brgs - - pts[1:0] pints[1:0] dps 00h ifcon interfa ce control register 8fh - cdpr - - - - - ispe 00h 4.1. accumulator acc is the accumulator register. most instructions use the accumulator to store the operand. mnemonic: acc address: e0h 7 6 5 4 3 2 1 0 reset acc.7 acc.6 acc05 acc.4 acc.3 acc.2 acc.1 acc. 0 00h acc[7:0]: the a (or acc) register is the standard 8052 accumulator. 4.2. b register the b register is used during multiply and divide instructions. it can also be used as a scratch pad register to store temporary data. mnemonic: b address: f0h 7 6 5 4 3 2 1 0 reset b.7 b.6 b.5 b.4 b.3 b.2 b.1 b.0 00h b[7:0]: the b register is the standard 8052 register that serves as a second accumulator.
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 21 - 4.3. program status word mnemonic: psw address: d0h 7 6 5 4 3 2 1 0 reset cy ac f0 rs [1:0] ov f1 p 00h cy : carry flag. ac: auxiliary carry flag for bcd operations. f0: general purpose flag 0 available for user. rs[1:0]: register bank select, used to select working register bank. rs[1:0] bank selected location 00 bank 0 00h ? 07h 01 bank 1 08h ? 0fh 10 b ank 2 10h ? 17h 11 bank 3 18h ? 1fh ov: overflow flag. f1: general purpose flag 1 available for user. p: parity flag, affected by hardware to indicate odd/even number of ?one? bits in the accumulator, i.e. even parity. 4.4. stack pointer the stack poin ter is a 1 - byte register initialized to 07h after reset. this register is incremented before push and call instructions, causing the stack to start from location 08h. mnemonic: sp address: 81h 7 6 5 4 3 2 1 0 reset sp [7:0] 07h sp[7:0]: the stack poin ter stores the scratchpad ram address where the stack begins. in other words, it always points to the top of the stack. 4.5. data pointer the data pointer (dptr) is 2 - bytes wide. the lower part is dpl, and the highest is dph. it can be loaded as a 2 - byte reg ister (e.g. mov dptr, #data16) or as two separate registers (e.g. mov dpl,#data8). it is generally used to access the external code or data space (e.g. movc a, @a+dptr, @dptr respectively). mnemonic: dpl address: 82h 7 6 5 4 3 2 1 0 reset dpl [7:0] 00h dpl[7:0]: data pointer low 0 mnemonic: dph address: 83h 7 6 5 4 3 2 1 0 reset dph [7:0] 00h dph [7:0]: data pointer high 0
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 22 - 4.6. data pointer 1 the dual data pointer accelerates the moves of data block. the standard dptr is a 16 - bit register that is used to address external memory or peripherals. in the sm39 r0 8a5 core the standard data pointer is called dptr; the second data pointer is called dptr1. the data pointer select bit chooses the active pointer. the data pointer select bit is located in lsb o f aux register (dps). the user switches between pointers by toggling the lsb of aux register. all dptr - related instructions use the currently selected dptr for any activity. dpl1[7:0]: data pointer low 1 mnemonic: dph1 address: 85h 7 6 5 4 3 2 1 0 reset dph1 [7:0] 00h dph1[7:0]: data pointer high 1 mnemonic: aux address: 91h 7 6 5 4 3 2 1 0 reset brgs - - pts[1:0] pints[1:0] dps 00h dps: data pointer selects register. dps = 1 is selected dptr1. 4.7. interface control register mnemonic: ifcon address: 8fh 7 6 5 4 3 2 1 0 reset - cdpr - - - - - ispe 00h cdpr: code protect (read only) ispe: isp function enable bit ispe = 1, enable isp function ispe = 0, disable isp function mnemonic: dpl1 address: 84h 7 6 5 4 3 2 1 0 reset dpl1 [7:0] 00h
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 23 - 5. gpio 5.1. sfr setting method the sm39 r0 8a5 has one i/o ports: port 3. these are quasi - bidirectional (standard 8051 port outputs), push - pull, open drain, and input - only. two configuration registers for each port select the output type for each port pin. all i/ o port pins on the sm39 r0 8a5 may be configured by software to one of four types on a pin - by - pin basis, shown as below: mnemonic description direct bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset i/o port function register p3m0 port 3 output mode 0 dah p3m0[7:0] 00h p3m1 port 3 output mode 1 dbh p3m1[7:0] 00h pxm1.y pxm0.y port output mode 0 0 quasi - bidirectional (standard 8051 port outputs) (pull - up) 0 1 push - pull 1 0 input only (high - impedance) 1 1 open drain the reset pin c an b e configur ed as i/o port p3.6 , when the user use s on- chip hardware reset mechanism . for general - purpose applications, every pin can be assigned to either high or low independently as given below: mnemonic description direct bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset ports port 3 port 3 b0h p3.7 p3.6 p3.5 p3.4 p3.3 p3.2 p3.1 p3.0 ffh mnemonic: p3 address: b0h 7 6 5 4 3 2 1 0 reset p3.7 p3.6 p3.5 p3.4 p3.3 p3.2 p3.1 p3.0 ffh p3.7~ 0: port3 [7] ~ port3 [0] 5.2. software of writer setting method please setting the ?io output mode" item in the "configuration" window, it can change the i/o mode of p3 to the ? quasi - bidirectional (standard 8051 port outputs) (pull - up)? or input only (high - impedance) mode, when mcu after reset and initial. it is supported th e version e of mcu after.
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 24 - 6. timer 0 and timer 1 the sm39 r08a5 has two 16 - bit timer/counter registers: timer 0 and timer 1. all can be configured for counter or timer operations. in timer mode, the timer 0 register or timer 1 register is incremented every 12 machine cycles, which means that it counts up after every 12 periods of the clock signal. in counter mode, the register is incremented when the falling edge is observed at the corresponding input pin t0or t1. since it takes 2 machine cycles to recogniz e a 1 - to - 0 event, the maximum input count rate is 1/2 of the oscillator frequency. there are no restrictions on the duty cycle, however to ensure proper recognition of 0 or 1 state, an input should be stable for at least 1 machine cycle. four operating mo des can be selected for timer 0 and timer 1. two special function registers (tmod and tcon) are used to select the appropriate mode. mnemonic description direct bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset timer 0 and 1 tl0 timer 0 , low byte 8 ah tl0[7:0] 00h th0 timer 0 , high byte 8ch th0[7:0] 00h tl1 timer 1 , low byte 8bh tl1[7:0] 00h th1 timer 1 , high byte 8dh th1[7:0] 00h tmod timer mode control 89h gate c/t m1 m0 gate c/t m1 m0 00h tcon timer/counter control 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00h aux auxiliary register 91h brgs - - pts[1:0] pints[1:0] dps 00h 6.1. timer/counter mode control register (tmod) mnemonic: tmod address: 89h 7 6 5 4 3 2 1 0 reset gate c/t m1 m0 gate c/t m1 m0 00h timer 1 timer 0 gate: if set, enables e xternal gate control (pin int0 or int1 for counter 0 or 1, respectively). when int0 or int1 is high, and trx bit is set (see tcon register), a counter is incremented every falling edge on t0 or t1 input pin c/t: selects timer or counter operation. when se t to 1, a counter operation is performed, when cleared to 0, the corresponding register will function as a timer. m[1:0]: selects mode for timer/counter 0 or timer/counter 1. m1 m0 mode function 0 0 mode0 13 - bit counter/timer, with 5 lower bits in tl0 or tl1 register and 8 bits in th0 or th1 register (for timer 0 and timer 1, respectively). the 3 high order bits of tl0 and tl1 are hold at zero. 0 1 mode1 16 - bit counter/timer. 1 0 mode2 8 - bit auto - reload counter/timer. the reload value is kept in th0 or th1, while tl0 or tl1 is incremented every machine cycle. when tlx overflows, a value from thx is copied to tlx. 1 1 mode3 if timer 1 m1 and m0 bits are set to 1, timer 1 stops. if timer 0 m1 and m0 bits are set to 1, timer 0 acts as two independent 8 bi t timers / counters.
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 25 - 6.2. timer/counter control register (tcon) mnemonic: tcon address: 88h 7 6 5 4 3 2 1 0 reset tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00h tf1: timer 1 overflow flag set by hardware when timer 1 overflows. this flag can be cleared by softw are and is automatically cleared when interrupt is processed. tr1: timer 1 run control bit. if cleared, timer 1 stops. tf0: timer 0 overflow flag set by hardware when timer 0 overflows. this flag can be cleared by software and is automatically cleared wh en interrupt is processed. tr0: timer 0 run control bit. if cleared, timer 0 stops. ie1: interrupt 1 edge flag. set by hardware, when falling edge on external pin int1 is observed. cleared when interrupt is processed. it1: interrupt 1 type control bit. selects falling edge or low level on input pin to cause interrupt. ie0: interrupt 0 edge flag. set by hardware, when falling edge on external pin int0 is observed. cleared when interrupt is processed. it0: interrupt 0 type control bit. selects falling ed ge or low level on input pin to cause interrupt. 6.3. enhance interrupt trigger sfr(enhit) mnemonic : enhit address : e5h 7 6 5 4 3 2 1 0 reset - enhit1 - enhit0 - - - - 07h note : it is supported the version e of mcu after. enhit0=0 enhit0=1 it0=0 int0 low level trigger i n t 0 low level trigger it0=1 int0 failing edge trigger int0 rising edge trigger enhit1 : interrupt 1 edge trigge r control bit. when enhit1 is set to 0 and it1 is set to 1 , the method of edge trigger is falling edge trigger. when enhit1 and it1 both are set to 1 , the method of edge trigger is rising edge trigger.
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 26 - 6.4. t0 the t0 t1 signal can be configured to other i/o . mnemonic: aux address: 91h 7 6 5 4 3 2 1 0 reset brgs - - pts [1:0] pints[1:0] dps 00h pts [1:0] t0 t1 0x00 - - 0x01 p3.3 p3.2 0x10 p3.0 p3.1 0x11 - -
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 27 - 7. serial interface the serial buffer consists of two separate registers, a transmit buffer and a receive buffer. writing data to the special function register s buf sets this data i n serial output buffer and starts the transmission. reading from the s buf reads data from the serial receive buffer. the serial port can simultaneously transmit and receive data. it can also buffer 1 byte at receive, which prevents the receive data from be ing lost if the cpu reads the first byte before transmission of the second byte is completed. mnemonic description direct bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset serial interface pcon power control 87h smod - - - - - stop idle 40h aux aux iliary register 91h brgs - - pts[1:0] pints[1:0] dps 00h scon serial port control register 98h sm0 sm1 sm2 ren tb8 rb8 ti ri 00h sbuf serial p ort data buffer 99h sbuf[7:0] 00h srell serial port reload register low byte aah s rel .7 s rel .6 s rel .5 s rel .4 s rel .3 s rel .2 s rel .1 s rel .0 00h srelh serial port reload register high byte bah - s rel .9 s rel .8 00h mnemonic: aux address: 91h 7 6 5 4 3 2 1 0 reset brgs - - pts[1:0] pints[1:0] dps 00h brgs: brgs = 0 ? baud rate generator use timer 1 th1 s fr. brgs = 1 ? baud rate generator use s rel sfr. mnemonic: s con address: 98h 7 6 5 4 3 2 1 0 reset sm0 sm1 sm2 ren tb8 rb8 ti r i 00h sm0,sm1: serial port mode selection. sm0 sm1 mode 0 0 0 0 1 1 1 0 2 1 1 3 the 4 modes in uart , mode 0 ~ 3, are ex plained later. sm2 : enables multiprocessor communication feature ren : if set, enables serial reception. cleared by software to disable reception. tb8 : the 9 th transmitted data bit in modes 2 and 3. set or cleared by the cpu depending on the function it performs such as parity check, multiprocessor communication etc. rb8 : in modes 2 and 3, it is the 9 th data bit received. in mode 1, if sm 2 is 0, rb8 is the stop bit. in mode 0, this bit is not used. must be cleared by software. ti : transmit interrupt fl ag, set by hardware after completion of a serial transfer. must be cleared by software. ri : receive interrupt flag, set by hardware after completion of a serial reception. must be cleared by software.
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 28 - the serial interface can operate in the following 4 modes: sm0 sm1 mode description board rate 0 0 0 shift register fosc/12 0 1 1 8 - bit uart variable 1 0 2 9 - bit uart fosc/32 or fosc/64 1 1 3 9 - bit uart variable here fosc is the crystal or oscillator frequency. 7.1. mode 0 pin rxd serves as input and o utput. txd outputs the shift clock. 8 bits are transmitted with lsb first. the baud rate is fixed at 1/12 of the crystal frequency. reception is initialized in m ode 0 by setting the flags in scon as follows: ri = 0 and ren = 1. in ot her modes, a start bit when ren = 1 starts receiving serial data. fig. 7 - 1: transmit mode 0 fig. 7 - 2: receive mode 0 7.2. mode 1 pin rxd serves as input, and txd serves as serial output. no external shift clock is used, 10 bits are transmitted: a start bit (always 0), 8 data bits (lsb first), and a stop bit (always 1). on receive, a start bit synchronizes the transmission, 8 data bits are available by reading s buf, and stop bit sets the flag rb8 in the special function register s con. in mode 1 either internal baud rate generat or or timer 1 can be use to specify baud rate. fig. 7 - 3: transmit mode 1
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 29 - fig. 7 - 4: receive mode 1 7.3. mode 2 this mode is similar to mode 1, with two differences. the baud rate is fixed at 1/32 (smod=1) or 1/64(smod=0) of oscillator frequency and 11 bi ts are transmitted or received: a start bit (0), 8 data bits (lsb first), a programmable 9 th bit, and a stop bit (1). the 9 th bit can be used to control the parity of the serial inte rface: at transmission, bit tb8 in s con is output as the 9 th bit, and at r eceive, the 9 th bit affects rb8 in special funct ion register s con. 7.4. mode 3 the only difference between mode 2 and mode 3 is that in mode 3 either internal baud rate generator or timer 1 can be use to specify baud rate. fig. 7 - 5: transmit modes 2 and 3 fig. 7 - 6: receive modes 2 and 3 7.5. multiprocessor communication the feature of receiving 9 bits in mod es 2 and 3 of serial interface can be used for multiprocessor communication. in this case, th e slave processors have bit sm2 in s con. when the master p rocessor outputs slave?s address, it sets the 9 th bit to 1, causing a serial port receive interrupt in all the slaves. the slave processors compare the received byte with their network address. if there is a match, the addressed slave will clear sm2 and re ceive the rest of the message, wh ile other slaves will leave sm2 bit unaffected and ignore this message. after addressing the slave, the host will output the rest of the message with the 9 th bit set to 0, so no serial port receive interrupt will be generat ed in unselected slaves.
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 30 - 7.6. baud rate generator serial interface modes 1 and 3 (a) when brgs = 0 (in sfr aux): ( ) th1 256 12 32 f 2 rate baud smod ? = osc (b) when brgs = 1 (in sfr aux): ( ) srel 2 64 f 2 rate baud 10 osc smod ? =
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 31 - 8. watchdog timer the watch dog timer (wdt) is an 8 - bit free - r unning counter that generate reset signal if the counter overflows. the wdt is useful for systems which are susceptible to noise, power glitches, or electronics discharge which causing software dead loop or runaway. the wdt function can help user software recover from abnormal software condition. the wdt is different from timer0, timer1 of general 8052. to prevent a wdt reset can be done by software periodically clearing the wdt counter. user should check wdtf bit of wdtc register whenever un - predicted rese t happened. after an external reset the watchdog timer is disabled and all registers are set to zeros. the watchdog timer has a free running on - chip rc oscillator ( 2 3 khz). the wdt will keep on running even after the system clock has been turned off (for example, in sleep mode). during normal operation or sleep mode, a wdt time - out (if enabled) will cause the mcu to reset. the wdt can be enabled or disabled any time during the normal mode. please refer the wdte bit of wdtc register. the default wdt time - ou t period is approximately 178.0 ms (wdtm [3:0] = 0100b). the wdt has selectable divider input for the time base source clock. to select the divider input, the setting of bit3 ~ bit0 (wdtm [3:0]) of watch dog timer control register (wdtc) should be set acco rdingly. wdtm 2 23khz = wdtclk watchdog reset time = wdtclk 256 table 8.1 wdt time - out period wdtm [3:0] divider (2 3 khz rc oscillator in) time period @ 2 3 khz 0000 1 1 1.1 ms 0001 2 22.2 ms 0010 4 44.5 ms 0011 8 89. 0 ms 0100 16 178.0 ms ( default) 0101 32 356.1 ms 0110 64 712.3 ms 0111 128 1. 4246 s 1000 256 2.8493 s 1001 512 5.6987 s 1010 1024 11.397 s 1011 2048 22.795 s 1100 4096 45.590 s 1101 8192 91.180 s 1110 16384 182.36 s 1111 32768 364.72 s note: rc oscillator (23 khz), about 20% of varia tion when mcu is reset, the mcu will be read wdten control bit status. when wdten bit is set to 1, the watchdog function will be disabled no matter what the wdte bit status is. when wdten bit is clear to 0, the watchdog function will be enabled i f wdte bit is set to 1 by program. user can to set wdten on the writer or isp. the program can enable the wdt function by programming 1 to the wdte bit premise that wdten control bit is clear to 0. after wdte set to 1, the 8 bit - counter starts to count wi th the selected time base source clock which set by wdtm [3:0]. it will generate a reset signal when overflows. the wdte bit will be cleared to 0 automatically when mcu been reset, either hardware reset or wdt reset.
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 32 - once the watchdog is started it cannot be stopped. user can refreshed the watchdog timer to zero by writing 0x55 to watch dog timer refresh key (wdtk) register. this will clear the content of the 8 - bit counter and let the counter re - start to count from the beginning. the watchdog timer must be refreshed regularly to prevent reset request signal from becoming active. when watchdog timer is overflow, the wdtf flag will set to one and automatically reset mcu. the wdtf flag can be clear by software or external reset or power on reset. 23khz rc oscillator wdtm 2 1 wdtc takey (55, aa, 5a) wdtm[3:0] wdten enable/disable wdt wdt counter wdtclk wdtk (0x55) refresh wdt counter 1. power on reset 2. external reset 3. software write ?0? wdtf set wdtf = 1 clear wdtf = 0 wdt time-out reset enable wdtc write attribute wdt time-out select wdt time-out interrupt cwdtr = 0 cwdtr = 1 fig. 8 - 1: watchdog timer block diagram mnemonic description direct bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rst watchdog timer takey time access key register f7h takey [7:0] 00h wdtc watchdog timer control register b6h - cwdt r wdte - wdtm [3:0] 04h wdtk watchdog timer refresh key b7h wdtk[7:0] 00h rsts reset status register a1h - - - pdrf wdtf swrf lvrf porf 00h mnemonic: takey address: f7h 7 6 5 4 3 2 1 0 reset takey [7:0] 00h watchdog timer control register (wdtc) is read - only by default; software must write three specific values 55h, aah and 5ah sequentially to the takey register to enable the wdtc write attribute. that is: mov takey, #55h mov takey, #aah mov takey, #5ah
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 33 - mnemonic: rsts address: a1h 7 6 5 4 3 2 1 0 reset - - - pdrf wdtf swrf lvrf porf 00h wdtf: watchdog timer reset flag. when mcu is reset by watchdog, wdtf flag will be set to one by hardware. this flag clear by software. mnemonic: wdtc address: b6h 7 6 5 4 3 2 1 0 reset - cwdtr wdte - wdtm [3:0] 04h cwdtr: 0: watchdog reset 1: watchdog interrupt wdte: control bit used to enable watchdog timer. the wdte bit can be used only if wdten, the bit7 of information block op3, is "0". if the wdten bit is "0", then wdt can be disabled / enabled by t he wdte bit. 0: disable wdt. 1: enable wdt. the wdte bit is not used if wdten, the bit7 of information block op3, is "1". that is, if the wdten bit is "1", wdt is always disabled no matter what the wdte bit status is. the wdte bit can be read and written. wdtm [3:0]: wdt clock source divider bit. please see table 7.8.1 to reference the wdt time - out period. mnemonic: wdtk address: b7h 7 6 5 4 3 2 1 0 reset wdtk[7:0] 00h wdtk: watchdog timer refresh key. a programmer must write 0x55 into wdtk register, and then the watchdog timer will be cleared to zero. for example, if enable wdt and select time - out reset period is 2 .8493 s. first, programming the information block op3 bit7 wdten to ?0?. secondly, mov takey, #55h mov takey, #aah mov takey, #5ah ; enab le wdtc write attribute. mov wdtc, #28h ; set wdtm [3:0] = 1000b. set wdte =1 to enable wdt ; function. . . . mov wdtk, #55h ; clear wdt timer to 0.
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 34 - for example 2, if enable wdt and select tim e - out interrupt period is 178.0m s. first, programming the inf ormation block op3 bit7 wdten to ?0?. secondly, mov takey, #55h mov takey, #0aah mov takey, #5ah ; enable wdtc write attribute. mov wdtc, #64h ; set wdtm [3:0] = 01 00b. set wdte =1 to enable wdt function ; and set cwdtr =1 to enable period interrupt function
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 35 - 9. interrupt the sm39 r 08a5 provides 11 interrupt sources with four priority levels. each source has its own request flag(s) located in a special function register. each interrupt requested by the corresponding flag could individually be enabled or disabled by the enable bits in sfr?s ien0, and ien1. when the interrupt occurs, the engine will vector to the predetermined address as shown in table 9.1. once interrupt service has begun, it can be interrupted only by a higher priority interrupt. the interrupt service is terminated by a return from instruction reti. when an reti is performed, the processor will return to the instruction that would have been next when interrupt occurred. when the interrupt condition occurs, the processor will also indicate this by setting a flag bit. this bit is set regardless of whether the interrupt is enabled or disabled. each interrupt flag is sampled once per machine cycle, and then samples are polled by hardware. if the sample indicates a p ending interrupt when the interrupt is enabled, then interrupt request flag is set. on the next instruction cycle the interrupt will be acknowledged by hardware forcing an lcall to appropriate vector address. interrupt response will require a varying amou nt of time depending on the state of microcontroller when the interrupt occurs. if microcontroller is performing an interrupt service with equal or greater priority, the new interrupt will not be invoked. in other cases, the response time depends on curren t instruction. the fastest possible response to an interrupt is 7 machine cycles. this includes one machine cycle for detecting the interrupt and six cycles for perform the lcall. table 9 - 1: interrupt vectors interrupt request flags interrupt vector addre ss interrupt number *(use keil c tool) ie0 ? external interrupt 0 0003h 0 tf0 ? timer 0 interrupt 000bh 1 ie1 ? external interrupt 1 0013h 2 tf1 ? timer 1 interrupt 001bh 3 ri/ti ? serial channel interrupt 0023h 4 pwmif ? pwm interrupt 0043h 8 adcif ? a/d converter interrupt 0053h 10 lviif ? low voltage interrupt 0063h 12 iicif ? iic interrupt 006bh 13 wdtif ? wdt interrupt 008bh 17 comparator interrupt 0093h 18 *see keil c about c51 user?s guide about interrupt function description
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 36 - m nemonic description direct bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rst interrupt aux auxiliary register 91h brgs - - pts[1:0] pints[1:0] dps 00h ien0 interrupt enable 0 register a8h ea - - es et1 ex1 et0 ex0 00h ien1 interrupt enable 1 register b8h - - ieiic ielvi - ieadc - iepw m 00h ien2 interrupt enable 2 register 9ah - - - - - ecmpi iewdt - 00h ircon interrupt request register c0h - - iicif lviif - adcif - pwmi f 00h ircon2 interrupt request register 2 97h - - - - - cmpif wdtif - 00h ip0 interrupt priority level 0 a9h - - ip0.5 ip0.4 ip0.3 ip0.2 ip0.1 ip0.0 00h ip1 interrupt priority level 1 b9h - - ip1.5 ip1.4 ip1.3 ip1.2 ip1.1 ip1.0 00h mnemonic: aux address: 91h 7 6 5 4 3 2 1 0 reset brgs - - pts[1:0] pints[1:0] dps 00h the int0 and int1 signal can be configured to other i/o. pints [1:0] int0 int1 0x00 - p3.7 0x01 - p3.5 interrupt enable 0 register (ien0) mnemonic: ien0 address: a8h 7 6 5 4 3 2 1 0 reset ea - - es et1 ex1 et0 ex0 00h ea: ea=0 ? disable all interrupt. ea =1 ? enable all interrupt. es : es=0 ? disable serial channel interrupt. es=1 ? enable serial channel interrupt. et1: et1=0 ? disable timer 1 overflow interrupt. et1=1 ? enable timer 1 overflow interrupt. ex1: ex1=0 ? disable external interrupt 1. ex1=1 ? enable external interrupt 1. et0: et0=0 ? disable timer 0 overflow interrupt. et0=1 ? enable timer 0 overflow interrupt. ex0: ex0=0 ? disable external interrupt 0. ex0=1 ? enable external interrupt 0.
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 37 - interrupt enable 1 register (ien1) mnemoni c: ien1 address: b8h 7 6 5 4 3 2 1 0 reset - - ieiic ielvi - ieadc - iepwm 00h ielvi: lvi interrupt enable. ielvi = 0 ? disable lvi interrupt. ielvi = 1 ? enable lvi interrupt. ieiic: iic interrupt enable. ieiics = 0 ? disable iic interrupt. ieiics = 1 ? enable iic interrupt. ieadc: a/d converter interrupt enable ieadc = 0 ? disable adc interrupt. ieadc = 1 ? enable adc interrupt. iepwm: pwm interrupt enable. iepwm = 0 ? disable pwm interrupt. iepwm = 1 ? enable pwm interrupt. interrupt enable 2 r egister (ien 2 ) mnemonic: ien2 address: 9ah 7 6 5 4 3 2 1 0 reset - - - - - ecmpi iewdt - 00h ecmpi: enable comparator 0 interrupt i ew dt: wdt interrupt enable. iewdt = 0 ? disable wdt interrupt. iewdt = 1 ? enable wdt interrupt. interrupt request re gister (ircon) mnemonic: ircon address: c0h 7 6 5 4 3 2 1 0 reset - - iicif lviif - adcif - pwmif 00h lviif: lvi interrupt flag. clear by hardware automatically iicif: iic interrupt flag. clear by hardware automatically adcif: a/d converter end inte rrupt flag. pwmif: pwm interrupt flag. clear by hardware automatically interrupt request register 2 (ircon 2 ) mnemonic: ircon2 address: 97h 7 6 5 4 3 2 1 0 reset - - - - - cmpif wdtif - 00h cmpif: comparator interrupt flag hw will clear this flag au tomatically when enter interrupt vector. sw can clear this flag also.(in case analog comparator int disable) wdtif: wdt interrupt flag.
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 38 - all interrupt sources are combined in groups: table 9 - 2: priority level groups groups external interrupt 0 - p wm interrupt timer 0 interrupt wdt interrupt - external interrupt 1 comparator interrupt adc interrupt timer 1 interrupt - - serial channel interrupt - lvi interrupt - - iic interrupt each group of interrupt sources can be programmed individuall y to one of four priority levels by setting or clearing one bit in the special fun ction register ip 0 and one in ip 1. if requests of the same priority level will be received simultaneously, an internal polling sequence determines which request is serviced f irst. mnemonic: ip0 address: a9h 7 6 5 4 3 2 1 0 reset - - ip0.5 ip0.4 ip0.3 ip0.2 ip0.1 ip0.0 00h mnemonic: ip1 address: b9h 7 6 5 4 3 2 1 0 reset - - ip1.5 ip1.4 ip1.3 ip1.2 ip1.1 ip1.0 00h table 9 - 3: priority levels ip1.x ip0.x priority level 0 0 level0 (lowest) 0 1 level1 1 0 level2 1 1 level3 (highest) table 9 - 4: groups of priority bit group ip1.0, ip0.0 external interrupt 0 - pwm interrupt ip1.1, ip0.1 timer 0 interrupt wdt interrupt - ip1.2, ip0.2 external interrupt 1 comparator in terrupt adc interrupt ip1.3, ip0.3 timer 1 interrupt - - ip1.4, ip0.4 serial channel interrupt - lvi interrupt ip1.5, ip0.5 - - iic interrupt
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 39 - table 9 - 5: polling sequence interrupt source sequence external interrupt 0 pwm interrupt ti mer 0 interrupt wdt interrupt external interrupt 1 comparator interrupt adc interrupt timer 1 interrupt serial channel interrupt lvi interrupt iic interrupt polling sequence
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 40 - 10. power management unit power management unit serves two power management modes, idle and stop, for the users to do power saving function. mnemonic: pcon address: 87h 7 6 5 4 3 2 1 0 reset smod - - - - - stop idle 40h stop: stop mode control bit. setting this bit turning on the stop mode. stop bit is always read as 0 idle: idle mode control bit. setting this bit turning on the idle mode. idle bit is always read as 0 10.1. idle mode setting the idle bit of pcon register invokes the idle mode. the idle mode leaves internal clocks and peripherals running. power consumption drops becau se the cpu is not active. the cpu can exit the idle state with any interrupts or a reset. 10.2. stop mode setting the stop bit of pcon register invokes the stop mode. all internal clocking in this mode is turn off. the cpu will exit this state only if interrup ts asserted from external int0/1 , lvi and wdt interrupt, or hardware reset by wdt and lvr.
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 41 - 11. pwm - pulse width modulation sm39 r 08a5 provides four - channel pwm outputs. the interrupt vector is 43h. mnemonic description direct bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset pwm pwmc pwm control register b5h pwmcs[2:0] - pwm3e n pwm2e n pwm1e n pwm0e n 00h pwmd0h pwm 0 data register high byte bch pwmp0 - - - - - pwmd0[9:8] 00h pwmd0l pwm 0 data register low byte bdh pwmd0[7:0] 00h pwmd1h pwm 1 data r egister high byte beh pwmp1 - - - - - pwmd1[9:8] 00h pwmd1l pwm 1 data register low byte bfh pwmd1[7:0] 00h pwmd2h pwm 2 data register high byte b1h pwmp2 - - - - - pwmd2[9:8] 00h pwmd2l pwm 2 data register low byte b2h pwmd2[7:0] 00h pwmd3h pwm 3 d ata register high byte b3h pwmp3 - - - - - pwmd3[9:8] 00h pwmd3l pwm 3 data register low byte b4h pwmd3[7:0] 00h pwmmdh pwm max data register high byte ceh - - - - - - pwmmd[9:8] 00h pwmmdl pwm max data register low byte cfh pwmmd[7:0] ffh mnemonic: pwmc address: b5h 7 6 5 4 3 2 1 0 reset pwmcs[2:0] - pwm3en pwm2en pwm1en pwm0en 00h pwmcs[2:0]: pwm clock select. pwmcs [2:0] mode 000 fosc 001 fosc/2 010 fosc/4 011 fosc/6 100 fosc/8 101 fosc/12 110 timer 0 overflow 111 p3.4
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 42 - pwm3en: pwm c hannel 3 enable control bit. pwm3en = 1 ? pwm channel 3 enable. pwm3en = 0 ? pwm channel 3 disable. pwm2en: pwm channel 2 enable control bit. pwm2en = 1 ? pwm channel 2 enable. pwm2en = 0 ? pwm channel 2 disable. pwm1en: pwm channel 1 enable control bit. pwm1en = 1 ? pwm channel 1 enable. pwm1en = 0 ? pwm channel 1 disable. pwm0en: pwm 0 enable control bit. pwm0en = 1 ? pwm channel 0 enable. pwm0en = 0 ? pwm channel 0 disable. mnemonic: pwmd0h address: bch 7 6 5 4 3 2 1 0 reset pwmp0 - - - - - pwmd0 [9:8] 00h mnemonic: pwmd0l address: bdh 7 6 5 4 3 2 1 0 reset pwmd0[7:0] 00h pwmp0: pwm channel 0 idle polarity select. ?0? ? pwm channel 0 will idle low. ?1? ? pwm channel 0 will idle high. pwmd0[9:0]: pwm channel 0 data register. mnemonic: pwmd1 h address: beh 7 6 5 4 3 2 1 0 reset pwmp1 - - - - - pwmd1[9:8] 00h mnemonic: pwmd1l address: bfh 7 6 5 4 3 2 1 0 reset pwmd1[7:0] 00h pwmp1: pwm channel 1 idle polarity select. ?0? ? pwm channel 1 will idle low. ?1? ? pwm channel 1 will idle high. pwmd1[9:0]: pwm channel 1 data register. mnemonic: pwmd2h address: b1h 7 6 5 4 3 2 1 0 reset pwmp2 - - - - - pwmd2[9:8] 00h mnemonic: pwmd2l address: b2h 7 6 5 4 3 2 1 0 reset pwmd2[7:0] 00h pwmp2: pwm channel 2 idle polarity select. ?0? ? pwm channel 2 will idle low. ?1? ? pwm channel 2 will idle high. pwmd2[9:0]: pwm channel 2 data register.
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 43 - mnemonic: pwmd3h address: b3h 7 6 5 4 3 2 1 0 reset pwmp3 - - - - - pwmd3[9:8] 00h mnemonic: pwmd3l address: b4h 7 6 5 4 3 2 1 0 reset pwmd3[7: 0] 00h pwmp3: pwm channel 3 idle polarity select. ?0? ? pwm channel 3 will idle low. ?1? ? pwm channel 3 will idle high. pwmd3[9:0]: pwm channel 3 data register. mnemonic: pwmmdh address: ceh 7 6 5 4 3 2 1 0 reset - - - - - - pwmmd[9:8] 00h mnemon ic: pwmmdl address: cfh 7 6 5 4 3 2 1 0 reset pwmmd[7:0] ffh pwmmd[9:0]: pwm max data register. pwm count from 0000h to pwmmd[9:0]. when pwm count data equal pwmmd[9:0] is overflow. pwmpx = 0 & pwmdx = 00h low pwmx pwmpx = 0 & p wmdx 00h pwmx pwmpx = 1 & pwmdx = 00h high pwmx pwmpx = 1 & pwmdx 00h pwmx clock pwm 1 pwmmd period pwm + = clock pwm pwmdx pulse leader =
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 44 - 12. iic function the iic module uses the scl (cloc k) and the sda (data) line to communicate with external iic interface. its speed can be selected to 400kbps (maximum) by software setting the iicbr [2:0] control bit. the iic module provided 2 interrupts (rxif, txif). it will generate start, repeated start and stop signals automatically in master mode and can detects start, repeated start and stop signals in slave mode. the maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance of 400pf. the in terrupt vector is 6bh. mnemonic description direct bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rst iic function iicctl iic control register f9h iicen mss mas ab_en bf_en iicbr[2:0] 04h iics iic status register f8h - mpif laif rxif txif rxak txak r w,b b 00h iica1 iic address 1 register fah iica1[7:1] match1 or rw1 a0h iica2 iic address 2 register fbh iica2[7:1] match2 or rw2 60h iicrwd iic read/write register fch iicrwd[7:0] 00h iicebt iic enaable bus transaction fdh fu_en - 00h mnemonic: iicctl address: f9h 7 6 5 4 3 2 1 0 reset iicen mss mas ab_en bf_en iicbr[2:0] 04h iicen: enable iic module iicen = 1 is enable iicen = 0 is disable. mss: master or slave mode select. mss = 1 is master mode. mss = 0 is slave mode. *the software must set this bit before setting others register. mas: master address select (master mode only) mas = 0 is to use iica1. mas = 1 is to use iica2. ab_en: arbitration lost enable bit. (master mode only) if set ab_en bit, the hardware will check arbitration lo st. once arbitration lost occurred, hardware will return to idle state. if this bit is cleared, hardware will not care arbitration lost condition. set this bit when multi - master and slave connection. clear this bit when single master to single slave. bf_e n: bus busy enable bit. (master mode only) if set bf_en bit, hardware will not generate a start condition to bus until bf=0. clear this bit will always generate a start condition to bus when mstart is set. set this bit when multi - master and slave connectio n. clear this bit when single master to single slave.
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 45 - iicbr[2:0]: baud rate selection (master mode only), where fosc is the external crystal or oscillator frequency. the default is fosc/512 for users? convenience. iicbr[2:0] baud rate 000 fosc/32 001 fosc/64 010 fosc/128 011 fosc/256 100 fosc/512 101 fosc/1024 110 fosc/2048 111 fosc/4096 mnemonic: iics address: f8h 7 6 5 4 3 2 1 0 reset - mpif laif rxif txif rxak txak rw 00h mpif : the stop condition interrupt flag the stop condition oc curred and this bit will be set. software need to clear this bit laif: arbitration lost bit. (master mode only) the arbitration interrupt flag, the bus arbitration lost occurred and this bit will be set. software need to clear this bit rxif: the data rec eive interrupt flag (rxif) is set after the iicrwd (iic read write data buffer) is loaded with a newly receive data. txif: the data transmit interrupt flag (txif) is set when the data of the iicrwd (iic read write data buffer) is downloaded to the shift r egister. rxak: the acknowledge status indicate bit. when clear, it means an acknowledge signal has been received after the complete 8 bits data transmit on the bus. txak: the acknowledge status transmit bit. when received complete 8 bits data, this bit w ill set (noack) or clear (ack) and transmit to master to indicate the receive status. rw: master mode: bus busy bit if detect scl=0 or sda=0 or bus start, this bit will be set. if detect stop,this bit will be cleared. this bit can be cleared by software t o return ready state. slave mode: the slave mode read (received) or wrote (transmit) on the iic bus. when this bit is clear, the slave module received data on the iic bus (sda).(slave mode only) fig. 11 - 1: acknowledgement bit in the 9 th bit of a byte t ransmission
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 46 - mnemonic: iica1 address: fah 7 6 5 4 3 2 1 0 reset iica1[7:1] match1 or rw1 a0h r/w r or r/w slave mode: iica1[7:1]: iic address registers this is the first 7 - bit address for this slave module. it will be checked when an address (fr om master) is received match1: when iica1 matches with the received address from the master side, this bit will set to 1 by hardware. when iic bus gets or send first data, this bit will clear automatically. master mode: iica1[7:1]: iic address register s this 7 - bit address indicates the slave with which it wants to communicate. rw 1: this bit will be sent out as rw of the slave side if the module has set the mstart or rstart bit. it appears at the 8 th bit after the iic address as shown in fig. 14 - 2. it is used to tell the salve the direction of the following communication. if it is 1, the module is in master receive mode. if 0, the module is in master transmit mode. fig. 11 - 2: rw bit in the 8 th bit after iic address mnemonic: iica2 address: fbh 7 6 5 4 3 2 1 0 reset iica2[7:1] match2 or rw2 60h r/w r or r/w slave mode: iica2[7:1]: iic address registers this is the second 7 - bit address for this slave module. it will be checked when an address (from master) is received match2: when iica2 matches with the received address from the master side, this bit will set to 1 by hardware. when iic bus gets or send first data, this bit will clear automatically. master mode: iica2[7:1]: iic address registers this 7 - bit address indicates the slave with which it wants to communicate. rw 2: this bit will be sent out as rw of the slave side if the module has set the mstart or rstart bit. it is used to tell the salve the direction of the following communication. if it is 1, the module is in master rece ive mode. if 0, the module is in master transmit mode.
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 47 - mnemonic: iicrwd address: fch 7 6 5 4 3 2 1 0 reset iicrwd[7:0] 00h iicrwd[7:0]: iic read write data buffer. in receiving (read) mode, the received byte is stored here. in transmitting mode, the byte to be shifted out through sda stays here. mnemonic: iicebt address: fdh 7 6 5 4 3 2 1 0 reset fu_en - - - - - - 00h master mode 00: reserved 01: iic bus module will enable read/write data transfer on sda and scl. 10: iic bus module generate a start condition on the sda/scl, then send out address which is stored in the iica1/iica2(selected by mas control bit) 11: iic bus module generate a stop condition on the sda/scl. slave mode: 01: fu_en[7:6] should be set as 01 only. the other value is inhibited. notice: 1. fu_en[7:6] should be set as 01 before read/write data transfer for bus release; otherwise, scl will be locked (pull low). 2. fu_en[7:6] should be set as 01 after read/write data transfer for receiving a stop condition from bus master. 3. in transmit data mode (slave mode), the output data should be filled into iicrwd before setting fu_en[7:6] as 01. 4. fu_en[7:6] will be a uto - clear by hardware, so setting fu_en[7:6] repeatedly is necessary.
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 48 - 13. lvi ? low voltage interrupt the interrupt vector 63h. mnemonic description direct bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset watchdog timer rsts reset status register a 1h - - - pdrf wdtf swrf lvrf porf 00h lvc low voltage control register e6h lvi_en - lvre lvif - - lvis 20h mnemonic: rsts address: a1h 7 6 5 4 3 2 1 0 reset - - - pdrf wdtf swrf lvrf porf 00h pdrf: pad reset flag. when mcu is reset by reset pad, pdr f flag will be set to one by hardware. this flag clear by software. lvrf: low voltage reset flag. when mcu is reset by lvr, lvrf flag will be set to one by hardware. this flag clear by software. porf: power on reset flag. when mcu is reset by por, porf f lag will be set to one by hardware. this flag clear by software. mnemonic: lvc address: e6h 7 6 5 4 3 2 1 0 reset lvi_en - lvre lvif - - lvis [1:0] 20h lvi_en: low voltage interrupt function enable bit. lvi_en = 0 - disable low voltage detect function . lvi_en = 1 - enable low voltage detect function. lvre: external low voltage reset function enable bit. lvre = 0 - disable external low voltage reset function. lvre = 1 - enable external low voltage reset function. lvif: low voltage interrupt flag (rea d only) lvis lvi level select: 00: 1. 7 v 01: 2.60v 10: 3.2 v 11: 4.0 v
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 49 - 14. 10- bit analog - to - digital converter (adc) the sm39 r08a5 provides eight channels 10 - bit adc. the digital output data [9:0] were put into adcd [9:0]. the adc interrupt vector is 53h. mux high speed 10 bits adc module adcc1[7:0] avss avdd adc0 adc7 adc6 adc clock divider adcch[2:0] adccs[4:0] fosc start vdd vss adcd[9:0] adc_isr the adc sfr show as below: mnemonic description direct bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset adc adcc1 adc control register 1 abh adc7en adc6en adc5en adc4en adc3en adc2en adc1en adc0en 00h adcc2 adc contr ol register 2 ach start adjust - - - adcch[2:0] 00h adcdh adc data high byte adh adcdh [7:0] 00h adcdl adc data low byte aeh adcdl [7:0] 00h adccs adc clock select afh - - - adccs[4:0] 00h mnemonic: adcc1 address: abh 7 6 5 4 3 2 1 0 reset adc7en ad c6en adc5en adc4en adc3en adc2en adc1en adc0en 00h adc7en: adc channels 7 enable. adc7en = 1 ? enable adc channel 7 adc6en: adc channels 6 enable. adc6en = 1 ? enable adc channel 6 adc5en: adc channels 5 enable. adc5en = 1 ? enable adc channel 5
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 50 - adc4e n: adc channels 4 enable. adc4en = 1 ? enable adc channel 4 adc3en: adc channels 3 enable. adc3en = 1 ? enable adc channel 3 adc2en: adc channels 2 enable. adc2en = 1 ? enable adc channel 2 adc1en: adc channels 1 enable. adc1en = 1 ? enable adc channel 1 adc0en: adc channels 0 enable. adc0en = 1 ? enable adc channel 0 mnemonic: adcc2 address: ach 7 6 5 4 3 2 1 0 reset start adjust - - - adcch[2:0] 00h start: when this bit is set, the adc will be start conversion continuous. adjust: adjust the for mat of adc conversion data. adjust = 0: (default value) adc data high byte adcd [9:2] = adcdh [7:0]. adc data low byte adcd [1:0] = adcdl [1:0]. adjust = 1: adc data high byte adcd [9:8] = adcdh [1:0]. adc data low byte adcd [7:0] = a dcdl [7:0]. adcch[2:0]: adc channel select. adcch [2:0] channel 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 adjust = 0: mnemonic: adcdh address: adh 7 6 5 4 3 2 1 0 reset adcd[9] adcd[8] adcd[7] adcd[6] adcd[5] adcd[4] adcd[3] adcd[2] 00 h mnemonic: adcdl address: aeh 7 6 5 4 3 2 1 0 reset - - - - - - adcd[1] adcd[0] 00h adjust = 1: mnemonic: adcdh address: adh 7 6 5 4 3 2 1 0 reset - - - - - - adcd[9] adcd[8] 00h mnemonic: adcdl address: aeh 7 6 5 4 3 2 1 0 reset adcd[7] adcd[ 6] adcd[5] adcd[4] adcd[3] adcd[2] adcd[1] adcd[0] 00h adcd[9:0]: adc data register.
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 51 - mnemonic: adccs address: afh 7 6 5 4 3 2 1 0 reset - - - adccs[4] adccs[3] adccs[2] adccs[1] adccs[0] 00h adccs[4:0]: adc clock select. *the adc clock maximum 2 2.1184 mhz. *the adc conversion rate maximum 851 khz. adccs[4:0] adc clock(hz) clocks for adc conversion 00000 fosc /2 26 00001 fosc/4 52 00010 fosc /6 78 00011 fosc /8 104 00100 fosc /10 130 00101 fosc /12 156 00110 fosc /14 182 00111 fosc /16 208 01000 fosc /18 234 01001 fosc /20 260 01010 fosc /22 286 01011 fosc /24 312 01100 fosc /26 338 01101 fosc /28 364 01110 fosc /30 390 01111 fosc /32 416 10000 fosc /34 442 10001 fosc /36 468 10010 fosc /38 494 10011 fosc /40 520 10100 fosc /42 5 46 10101 fosc /44 572 10110 fosc /46 598 10111 fosc /48 624 11000 fosc /50 650 11001 fosc /52 676 11010 fosc /54 702 11011 fosc /56 728 11100 fosc /58 754 11101 fosc /60 780 11110 fosc /62 806 11111 fosc /64 832 ) 1 ( 2 fosc _ + = adccs clock adc 13 adc_clock _ _ = rate conversion adc
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 52 - 15. eeprom the sm39 r0 8a5 can generate flash control signal by internal hardware circuit. the sm39 r0 8a5 provides internal flash control signals which can do flash program/page erase functions. isp register ? takey, ifcon, ispfah, ispfal , ispfd and ispfc : mnemonic description direct bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset isp function takey time access key register f7h takey [7:0] 00h ifcon interface control register 8fh - cdpr - - - - - ispe 00h ispfah isp flash addres s - high register e1h ispfah [ 7 :0] ffh ispfal isp flash address - low register e2h ispfal [7:0] ffh ispfd isp flash data register e3h ispfd [7:0] ffh ispfc isp flash control register e4h - - - - - ispf.2 ispf.1 ispf.0 00h mnemonic: takey address: f7h 7 6 5 4 3 2 1 0 reset takey [7:0] 00h isp enable bit (ispe) is read - only by default, software must write three specific values 55h, aah and 5ah sequentially to the takey register to enable the ispe bit write attribute. that is: mov takey, #55h mov take y, # a a h mov takey, #5ah mnemonic: ifcon address: 8fh 7 6 5 4 3 2 1 0 reset - cdpr - - - - - ispe 00h the bit 0 (ispe) of ifcon is isp enable bit. user can enable overall sm39 r08a5 eeprom function by setting ispe bit to 1, to disable overall eeprom fun ction by set ispe to 0. the function of ispe behaves like a security key. user can disable overall isp function to prevent software program be erased accidentally. isp registers ispfah, ispfal, ispfd and ispfc are read - only by default. software must be set ispe bit to 1 to enable these 4 registers write attribute. mnemonic: ispfah address: e1h 7 6 5 4 3 2 1 0 reset ispfah 7 ispfah 6 ispfah 5 ispfah 4 ispfah3 ispfah2 ispfah1 ispfah0 ffh ispfah [ 7 :0]: flash address - high for eeprom function .
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 53 - mnemonic: i spfal address: e2h 7 6 5 4 3 2 1 0 reset ispfal7 ispfal6 ispfal5 ispfal4 ispfal3 ispfal2 ispfal1 ispfal0 ffh ispfal [7:0]: flash address - low for eeprom function . mnemonic: ispfd address: e3h 7 6 5 4 3 2 1 0 reset ispfd7 ispfd6 ispfd5 ispfd4 ispfd3 ispfd2 ispfd1 ispfd0 ffh ispfd [7:0]: flash data for byte programming function. mnemonic: ispfc address: e4h 7 6 5 4 3 2 1 0 reset - - - - - ispf[2] ispf[1] ispf[0] 00h ispf [2:0]: isp function select bit. ispf[2:0] isp function 000 byte progra m 010 page erase one page of flash memory is 128 byte the choice eeprom function will start to execute once the software write data to ispfc register. to perform byte program/page erases function, user need to specify flash address at first. when perf orming page erase function, sm39 r08a5 will erase entire page which flash address indicated by ispfah & ispfal registers located within the page. e.g. flash address: $ x ymn page erase function will erase from $ x y00 to $ x y 7f or $ x y 8 0 to $ x y ff e.g. isp ser vice program to do the byte program - t o program #22h to the address $ 1 0 05h mov takey, #55h mov takey, #0aah mov takey, #5ah ; enable ispe write attribute orl ifcon, #01h ; enable sm39r08a 5 eeprom function mov ispfah, #10h ; set flash address - high, 10h mov ispfal, #05h ; set flash address - low, 05h mov ispfd, #22h ; set flash data to be programmed, data = 22h mov ispfc, #00h ; start to program #22h to the flash address $1005h mov takey, #55h mov takey, #0aah mov takey, #5ah ; enable ispe write attribute anl ifcon, #0feh ; disable sm 39 r08a5 eeprom function
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 54 - 16. comparator sm39 r08a5 had integrated a comparator i n chip. this module supports comparator modes individually according to user?s configuration. when u se it as comparator, the comparator output is logical one when positive input greater than negative input, otherwise the output is a zero. mnemonic description addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset op/comparator oppin comparator pin select f6h - cmp0en c0pos vbg c0pos pad - - - - 00h cmp0con comparator 0 control feh hys0en cmp0o cmf0ms[1:0] cmf0 cmp0 outen - - 00h mnemonic: oppin address: f6h 7 6 5 4 3 2 1 0 reset - cmp0en c0posvbg c0pospad - - - - 00h cmp0en : cmp0 ena ble. 1: comparator_0 circuit enable and switch to corresponding signal in multi - function pin p 3 .0/p 3 .1/p 3 .7 by hw automatically. c0posvbg : select comparator_0 positive input source 1: set positive input source as internal reference voltage (1.2v 10 %) c0 pospad : select comparator_0 positive input source 1: set positive input source as external pin comparator setting table : cmp0en c0posvbg c0pospad cmp0outen comparator cmp0pin cmp0nin cmp0out 0 x x x io io io 1 0 0 x error error error 1 0 1 0 cm p cmp io 1 0 1 1 cmp cmp cmp 1 1 0 0 io cmp io 1 1 0 1 io cmp cmp 1 1 1 x error error error mnemonic: cmp0con address:feh 7 6 5 4 3 2 1 0 reset hys0en cmp0o cmf0ms[1:0] cmf0 cmp0 outen - - 00h hys0en : hysteresis function enable 0: disable hyster esis at comparator_0 input 1: enable cmp0o : comparator_0 output (read only) 0: the positive input source was lower than negative input source 1: the positive input source was higher than negative input source cmf0ms[1:0] : cmf0(comparator_0 flag) setti ng mode select 00: cmf0 will be set when comprator_0 output toggle 01: cmf0 will be set when comprator_0 output rising 10: cmf0 will be set when comprator_0 output falling 11: reserved cmf0 : comparator_0 flag
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 55 - this bit is setting by hardware according to meet cmf0ms [1:0] select condition. this bit must c lear by software. cmp0outen : comparator_0 output enable 0: comparator_0 will not output to external pin 1: comparator_0 will output to external pin
sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 56 - dc characteristics t a = - 40 to 85, v cc = 5.0v symbol parameter valid min typ max units conditions vil1 input low - voltage port 3 - 0.5 0.8 v vcc=5v vil2 input low - voltage res 0 0.8 v vih1 input high - voltage port 3 2.0 v cc + 0.5 v vih2 input high - voltage res 70%vcc v cc + 0.5 v vol output low - voltage p 3.0/p3.1/p3.4/p3.7 0.4 5 v iol= 20 ma vcc=5v p3.2/p3.3/p3.5/p3.6 0.4 5 v iol= 38 ma vcc=5v voh1 output high - voltage using strong pull - up (1) p3.0/p3.1/p3.4/p3.7 9 0%vcc v ioh= - 8 ma p3.2/p3.3/p3.5/p3.6 9 0%vcc v ioh= - 15ma voh2 output high - voltage using weak pull - up (2) port 3 2.4 v ioh= - 250ua iil logic 0 input current port 3 - 75 ua vin= 0.45v itl logical transition current port 3 - 650 ua vin= 2.0v ili input leakage current port 3 10 ua 0.45v sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 57 - t a = - 40 to 85, v cc = 3.0v symbol parameter valid min typ max units conditions vil1 input low - voltage port 0,1,3 - 0.5 0.8 v vcc=3.0v vil2 input low - voltage res, xtal1 0 0.8 v vih1 input high - voltage port 0,1,3 2.0 v cc + 0.5 v vih2 input high - voltage res, xtal1 70%vcc v cc + 0.5 v vol output low - voltage p 3.0/p3.1/p3.4/p3.7 0.4 5 v iol= 14 ma vcc= 3 v p3.2/p3.3/p3.5/p3.6 0.45 v iol= 15 ma vcc= 3 v voh1 output high - voltage using strong pull - up (1) p3.0/p3.1/p3.4/p3.7 9 0%vcc v ioh= - 5 ma p3.2/p3.3/p3.5/p3.6 9 0%vcc v ioh= - 10ma voh2 output high - voltage using weak pull - up (2) port 0,1,3 2.4 v ioh= - 77 ua iil logic 0 input cu rrent port 0,1,3 - 75 ua vin= 0.45v itl logical transition current port 0,1,3 - 650 ua vin=1.5v ili input leakage current port 0,1,3 10 ua 0.45v sm39r08 a 5 8 - bit micro - controller with 8kb fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m067 ver e sm 3 9 r 08a5 0 6/3 0 / 20 1 5 - 58 - adc characteristics s ymbol test con dition min typ max unit operation v dd v dd 2.7 5.5 v resolution 10 bit conversion time 13t adc us sample rate 870k hz integral non - linearity error inl - 1 1 lsb differential non - linearity dnl - 1 1 lsb clock frequency adcclk 11.36 - 5. 25 mhz comparator characteristics ta=25 symbol description test condition min tpy max unit v dd condition i op o perating current 5 - - 10 10 ua - power down current 5 - - - 0.1 ua - o ffset voltage 5 - - 10 - +10 mv v cm i nput voltage commom mode range - - vss - vdd - 1.5 v tp propag ation delay 5 vin=10mv - 3 6 us l vi& l vr characteristics lvr min typical max 1.8v ~ 5.5v vil=1.4v vil=1.5v vil=1. 6 v lvi min typical max lvis[1:0] = 00 vil=1. 6 v vil=1. 7 v vil=1. 8 v lvis[1:0] = 01 vil=2. 5 v vil=2.6v vil=2.7v lvis[1:0] = 10 vil =3. 1 v vil=3.2v vil=3.3v lvis[1:0] = 11 vil=3. 9 v vil=4.0v vil=4. 1 v notes : the v lvi always above v lvr about 0.2v

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